1. Field of the Invention
The present invention generally relates to an SIMD (single instruction stream multiple data stream) type microprocessor which processes multiple data in parallel by a single arithmetic instruction.
2. Description of the Related Art
Since an SIMD type microprocessor can simultaneously apply the same arithmetic process to multiple data elements by a single instruction, in many cases, the SIMD type microprocessor is used to process image data.
The SIMD type microprocessor provides plural PEs (processor elements) each of which has an arithmetic circuit and a register. In the SIMD type microprocessor, since the plural PEs simultaneously execute the arithmetic processes, the image processing efficiency is high. Generally, one PE executes the image process of one pixel. Since the SIMD type microprocessor provides the plural PEs, the image processes of the plural pixels can be simultaneously executed.
Image data are handled as an aggregate in which data are two-dimensionally arranged. For example, when X data elements (X is an integer) are arranged in the horizontal direction and Y data elements (Y is an integer) are arranged in the vertical direction, in an array of PEs, data are arranged in one of the horizontal and vertical directions corresponding to the array of the PEs. For example, when each PE processes image data based on the array in the horizontal direction, one image data element in the horizontal direction is arranged in each PE, and the image data are processed.
In addition, for example, when a filter process is applied to image data, since an arithmetic process is executed by referring to image data positioned adjacently, the arrangement of the PEs must have a close relationship with the arrangement of the image data.
When a first PE is defined as PE0, a second PE is defined as PE1, a third PE is defined as PE2, and similarly an mth PE is defined as PE(m−1), and a first image data element is defined as PIXEL0, a second image data element is defined as PIXEL1, a third image data element is defined as PIXEL2, and similarly an mth image data element is defined as PIXEL(m−1), the number attached to the PE coincides with the number attached to the image data element.
In a case where image data are arbitrarily designated, when a PE where the image data are arranged is designated, the image data are designated. That is, for example, when PIXEL8 through PIXEL15 are desired to be designated, it is equivalent that PE8 through PE15 are designated. In a case where image data are processed, when a range of the image data to be processed must be designated, the range is designated by specifying the PE numbers.
In a conventional SIMD type microprocessor, since one image data element is arranged in one PE, the image data element can be easily designated by specifying the number of the PE. In an SIMD type microprocessor in Patent Document 1, plural image data elements are arranged in one PE. Patent Document 1 does not teach the designation of a range of image data to be processed; however, when a conventional circuit is used, the range of the image data to be processed can be designated by specifying the PE numbers.    [Patent Document 1] Japanese Laid-Open Patent Application No. 2006-260479
However, as described in Patent Document 1, when the plural image data elements are arranged in one PE, two or more arranging methods exist by a relationship between the order of the image data and the order of the PEs. When a range of the image data to be processed is designated, an optimal designation may be assumed in each arrangement of the image data. However, Patent Document 1 does not teach the designation of the range of the image data to be processed.
For example, when the number of PEs is 256 and two image data elements are arranged in one PE, two arrays of the image data can be assumed.
In a first array, two sets of 256 sequential image data elements are arranged. For example, image data of different two lines are arranged. In a first set, one image data element is arranged in one PE, and 256 image data elements are arranged in the corresponding PEs in order. Similarly, in a second set, one image data element is arranged in one PE, and 256 image data elements are arranged in the corresponding PEs in order. The two image data elements are arranged in one PE; that is, one image data element from the first array and one image data element from the second array are arranged in one PE.
At this time, in each PE, the image data in the first set are determined to be lower side image data, the image data in the second set are determined to be upper side image data, and circuits such as registers and arithmetic circuits are allocated to each PE corresponding to the upper side image data and the lower side image data. When a range of image data to be processed is designated in the first array, a conventional rule can be used in which the image data are designated by specifying the numbers of the PEs. For example, when the image data of PIXEL8 through PIXEL15 are designated, PE8 through PE15 are specified. At this time, the range of the image data to be processed in the first set is the same as the range of the image data to be processed in the second set. This causes a restriction in programming for the image processing.
When image processing is desired to be differently applied to each of the two lines of data (data string), software must be prepared so as to, for example, move a position of a register where image data are stored so that different data strings are not to be processed at the same time. That is, in the first array, an individual range of the image data to be processed cannot be designated in each of the first set and the second set.
In a second array, one set of 512 sequential image data elements is arranged. Two image data elements are arranged in one PE in order so that the two image data sets of the small numbers of PIXELs are arranged in the small number of PEs and the two image data sets of the large numbers of PIXELs are arranged in the large number of PEs.
In each PE, the image data whose PIXEL number is small are determined to be lower side image data, the image data whose PIXEL number is large are determined to be upper side image data, and circuits such as registers and arithmetic circuits are allocated to each PE. When a range of image data to be processed is designated in the second array and the conventional rule is used in which the image data are designated by specifying the number of PEs, since the two image data elements arranged in the one PE are in the same range, a different boundary between the ranges of the two image data elements cannot be determined. Consequently, the two image data elements are processed as one unit. This causes a restriction in programming for the image processing.
Basically, one image data set is desired to be processed as one unit; however, since the two image data sets are processed as one unit, the accuracy of the image processing is decreased and the image quality may be degraded.
That is, in the conventional method, in the SIMD type microprocessor which handles the image data of the plural pixels in one PE, a restriction occurs in programming for the image processing which desires to designate the range of the image data to be processed.